Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device including a data output strobe signal generation circuit.
Generally, semiconductor devices, specifically double data rate synchronous DRAMs (DDR SDRAMs), are configured to receive an external clock signal to generate an internal clock signal. A delay within a semiconductor device may cause a clock skew between an external clock signal and an internal clock signal. Therefore, a clock synchronization circuit for compensating for the clock skew is provided within the semiconductor device. Representative examples of the clock synchronization circuit are a phase locked loop (PLL) and a delay locked loop (DLL).
The internal clock signal generated in this manner is inputted to several circuits within the semiconductor device and used as a reference for the respective circuits.
Meanwhile, the semiconductor memory device includes a data output buffer for a data output operation. The data output buffer is configured to output data transferred through global input/output lines in synchronism with a data output strobe signal. The data output strobe signal is generated from a rising clock signal having a high duration at a rising edge time of a DLL clock signal, or a falling clock signal having a high duration at a falling edge time of a DLL clock signal. To this end, a data output strobe signal generation circuit is provided.
FIG. 1 is a block diagram of a typical data output circuit.
Referring to FIG. 1, the typical data output circuit includes a delay locked loop 110, a data output strobe signal generation unit 130, and a data output unit 150.
The delay locked loop 110 is configured to receive an external clock signal CLK_EXT to generate a rising DLL clock signal RCLK_DLL which is synchronized with a rising edge of the external clock signal CLK_EXT and is compensated for clock skew, and a falling DLL clock signal FCLK_DLL which is synchronized with a falling edge of the external clock signal CLK_EXT and is compensated for clock skew.
The data output strobe signal generation unit 130 is configured to receive the rising DLL clock signal RCLK_DLL and the falling DLL clock signal FCLK_DLL to generate data output strobe signals RCLK_DO, RCLK_DOB, FCLK_DO and FCLK_DOB.
The data output unit 150 is configured to receive data signals (not shown) and output a data signal as a final output data DATA in synchronism with the data output strobe signals.
FIG. 2 is a detailed block diagram of the data output strobe signal generation unit 130 illustrated in FIG. 1.
The data output strobe signal generation unit 130 receives a rising data enable signal ROUTEN and a falling data enable signal FOUTEN in order to generate the data output strobe signals RCLK_DO, RCLK_DOB, FCLK_DO and FCLK_DOB. The rising data enable signal ROUTEN is an enable signal which is activated from a logic low level to a logic high level so that data is outputted at a rising time of a clock, and the falling data enable signal FOUTEN is an enable signal which is activated from a logic low level to a logic high level at a falling time of a clock.
Referring to FIG. 2, the data output strobe signal generation unit 130 includes a first NAND gate 131, a first inverter 132, a second inverter 133, a second NAND gate 135, a third inverter 136, and a fourth inverter 137. The first NAND gate 131 is configured to receive a NAND operation on the rising DLL clock signal RCLK_DLL and the rising data enable signal ROUTEN and perform a NAND operation on the received signals RCLK_DLL and ROUTEN. The first inverter 132 is configured to receive an output signal of the first NAND gate 131, invert a phase of the output signal of the first NAND gate 131, and output the first rising strobe signal RCLK_DO.
The second inverter 133 is configured to receive an output signal of the first inverter 132, invert a phase of the output signal of the first inverter 132, and output the second rising strobe signal RCLK_DOB. The second NAND gate 135 is configured to receive the falling DLL clock signal FCLK_DLL and the falling data enable signal FOUTEN and perform a NAND operation on the received signals FCLK_DLL and FOUTEN. The third inverter 136 is configured to receive an output signal of the second NAND gate 135, invert a phase of the output signal of the second NAND gate 135, and output the first falling strobe signal FCLK_DO. The fourth inverter 137 is configured to receive an output signal of the third inverter 136, invert a phase of the output signal of the third inverter 136, and output the second falling strobe signal FCLK_DOB.
That is, the second rising strobe signal RCLK_DOB is generated by inverting the first rising strobe signal RCLK_DO, and the second falling strobe signal FCLK_DOB is generated by inverting the first falling strobe signal RCLK_DOB. Therefore, the second rising strobe signal RCLK_DOB is delayed by a delay amount corresponding to one inverter, relative to the first rising strobe signal RCLK_DO, and the second falling strobe signal FCLK_DOB is delayed by a delay amount corresponding to one inverter, relative to the first falling strobe signal FCLK_DO.
FIG. 3 is a detailed circuit diagram of the data output unit 150 illustrated in FIG. 1.
Referring to FIG. 3, the data output unit 150 is configured to output a first data signal RDO as a final output data DATA in response to the first rising strobe signal RCLK_DO and the second rising strobe signal RCLK_DOB, and output a second data signal FDO as the final output data DATA in response to the first falling strobe signal FCLK_DO and the second falling strobe signal FCLK_DOB. Accordingly, a final data DATA is outputted from the data output unit 150.
As illustrated in FIG. 4, the data output unit 150 receives the first rising strobe signal RCLK_DO and the second rising strobe signal RCLK_DOB having opposite phases to each other to output the first data signal RDO, and receives the first falling strobe signal FCLK_DO and the second falling strobe signal FCLK_DOB having opposite phases to each other to output the second data signal FDO.
In this case, the first data signal RDO and the second data signal FDO are alternately outputted. However, as illustrated in FIG. 4, since the rising time and the falling time of the respective strobe signals are different, Vox is large and a data valid window (tDV) is small. Vox (deviation of the output cross point voltage from the termination voltage) represents a voltage difference between a cross point voltage of the strobe signals used during data output and half the power supply voltage (VDD/2) used for driving the data output unit 150.
Thus, distorted data have been outputted. That is, it may be difficult to output data having a stable voltage level at a desired timing, causing degradation in the performance of the semiconductor device.